In recent years, demands have been increasing for higher reliability and more reduction in size and weight of electronic devices. Electronic components such as transistors, diodes, ICs (Integrated Circuits), resistors, capacitors and connectors as well as electrode pads and leads for mounting boards (interposers and print circuit boards) for mounting the electronic components are becoming finer and provided with narrower pitch spacing than ever.
In particular, solder joints of ICs, BGAs (Ball Grid Arrays), semiconductor apparatuses and electronic apparatuses are facing demands for an extremely high quality reliability, for said electronic components are tin- or solder-jointed to the mounting boards of ICs and BGAs, and electronic circuits in semiconductor apparatuses and electronic apparatuses are formed including CSPs (Chip Size Packages) soldered to the mounting boards with fine and narrow pitch spacing.
In view of the situation, also the tin or the solder alloy used for the tin or solder joints are demanded for more joint strength and high, long-term quality reliability. Particularly, remediation measures for the following problems that have come to the front are strongly demanded: reliability of fine tin or solder joints in keeping with the miniaturization of the junctions; a pad pitch spacing and a lead pitch spacing in electronic elements and electronic components; leakage failures caused by the excess volume of solder and the solder bridges particularly in a circuit pattern with a narrow pitch spacing; thermal fatigue resistance against the heat cycle fatigue due to heat cycle in solder joints caused by energization switching of electronic devices; and impact breaking resistance associated with the Kirkendall voids that are generated often in the vicinity of joint interfaces after a long-time high-temperature exposure (heat aging).
For one thing, it is needles to say that the trends for finer and narrower pitch also exist in solder joints. For example, mass production technology of fine circuits provided with electrode pads and leads up to 80 μm in width and up to 150 μm in pitch is strongly desired. Such a technology has been considered almost impossible in the conventional methods where soldering is performed by soaking in a molten solder liquid.
For another, in recent years, regulations or bans have been enforced on the use of lead because of its hazardous property. Especially, in the field of electronic components, a so-called “lead-free solder” containing no lead has begun to be commonly used in the latter half of 1990s. It has taken the place of the conventional tin-lead type solder since about the time when the RoHS (Restriction of Hazardous Substances) came into force, and has been rapidly put into practical use.
In such circumstances, a lead-free solder alloy of tin/silver/copper type, a solder alloy additionally added with antimony (Japanese Patent Application Publication No. H05-50286 (Japanese Patent No. 3027441)) and a solder alloy made from a solder alloy of tin/silver/copper type added with nickel or germanium (Japanese Patent Application Publication No. H11-77366 (Japanese Patent No. 3296289)) are, among others, widely in practical use. In addition, also in use are various lead-free solder alloys such as a solder alloy of tin/zinc/nickel type and a solder alloy additionally added with silver, copper, bismuth and so on (Japanese Patent Application Publication No. H09-94688 (Japanese Patent No. 3299091)).
On the other hand, in view of the historical achievement, the quality stability and the reliability, a 63 tin/lead solder (a eutectic solder with 63 mass % Sn and 37 mass % Pb) is partly used for joints of electronic components for automobiles and aircrafts as well as semiconductor devices and electronic devices to this day.
However, these actually-used tin or solder alloys generally contain several hundreds ppm of metallic oxide that makes the viscosity relatively high and the solderability relatively low when melted. Therefore, when solder-coating a fine circuit provided with electrode pads and leads up to 80 μm in width and up to 150 μm in pitch or when solder-plating a semiconductor or various fine electronic components such as BGAs or CSPs to mounting boards, the excessive amount of solder forms projections or so-called “excess volume” at the joints (in the form of horns or icicles in extreme cases. Or otherwise, they are adhered in convexed form because of the relatively big surface tension), even if an appropriate flux is used. Then, particularly where the neighboring pitch is narrow, solder bridges are formed toward the neighboring electrode pads or leads, which results in being subject to “leakage failure” problems. Also, unless an appropriate flux is used at the same time, there exist problems of a poor appearance such as partly “incomplete solderings” arising from the bad solderability.
Moreover, the conventional solder generally has relatively low stretchability (ductility) as one of the physical-mechanical characteristics of solder. Thus, after electronic circuits are built into semiconductor apparatuses or electronic apparatuses and repeatedly switched on and off, solder joints are fatigue-broken with time due to the heat cycle of the heat generation and standing to cool, and conduction failures occur. It is widely known that this impairs the connection reliability of miniaturized electronic devices (Japanese Patent Application Publication No. 2001-237536 (Japanese Patent No. 3221670)).
In other words, with the existing solder joint technique that uses a molten solder or that is performed by applying a solder paste and then melting it, quite a number of leakage failures occur due to said “excess solder” (horns or icicles) or solder bridges toward the adjacent leads. (In an electronic device, for example, the whole surface of the mounting board is coated with a protective film except where the electrode pads and the leads are disposed. Then, a metal mask with openings that are cut to match the electrode pads and leads is put on the mounting board, and the solder paste is printed on the electrode pads and the leads to a predetermined thickness by using a roller or a squeegee. After that, the metal mask is taken off, and the predetermined electronic components are automatically mounted on the predetermined positions of the electrode pads and the leads on the mounting board by an automatic surface mount machine or a mounter. By going through a reflow furnace heated to the temperature where the solder paste is melted and soldering is possible, various components are solder-jointed to the mounting board, and thus the electronic device is produced.) In the formation of minimum, narrowest and fine electronic circuit which can avoid the leakage failures and in which fine, narrow-pitched electrode pads and leads are stably solder-coated or solder-jointed, it is generally said that the minimum electrode pads and leads are about 80 μm in width and about 200 μm in pitch.
Therefore, when forming e.g. fine bumps on fine electrode pads of the chips for a CSP, a still finer and narrower-pitched electronic circuit is formed by coating the whole surface with a protective film except where the electrode pads, on which bumps are formed, are disposed, and then electroform gold or solder bumps to a thickness of some tens μm on the metal surface (that is generally Au-flash plated over the underlying Ni plating) of the perforated electrode pad. Likewise, in the case of mounting boards and BGAs, a fine electronic circuit is primarily formed by electroforming a tin or a solder alloy to a thickness of some tens to 100 μm. However, there are drawbacks such as that the gold is very expensive and that the electroformed solder is inefficient because it requires a long time, complex management, and high initial cost.
Furthermore, with the above-mentioned existing solder-coating and solder-jointing technique, it is generally essential to use a flux or a solder paste for the coating or the jointing. As a result, a solvent and a resin content contained in the flux or the solder paste instantaneously evaporate and scatter at the time of solder jointing, and often generate microvoids by partly remaining as microbubbles at the solder interface or within the solder joint. As a result of various technological improvements and innovations, there are methods for eliminating the microvoids nearly completely. However, with the existing solder joint technology, the Kirkendall voids are generated near the joint interface when the spots are exposed to a high temperature by cumulative energization over a long time (generally exposed at 100° C. or a higher temperature: so-called “heat aging”). The Kirkendall voids increase with time, and at an application of an impact force, the joints fracture. This has become a big problem in recent years from the point of view of the reliability of electronic devices (R. Aspandiar, “Void in Solder Joints”, SMTA Northwest Chapt. Meeting (Sep. 21, 2005); C. Hillman, “Long-term reliability of Pb-free electronics”, Electronic Products, p. 69 (September 2005); Mitsuyuki Ban, Yutaka Shimauchi, “Various Techniques for Reliability Estimation and Failure Analysis of Electronic Products and Components”, JFE Giho, No. 13, pp. 97-102 (August 2006); Shinji Ishikawa et al., “Generation of Kirkendall voids at joint between high-temperature solder and Cu board”, Journal of Japan Institute of Electronics Packaging, Vol. 9, No. 4, pp. 269-277 (2006)).
During the heat cycle in which high and low temperatures are generated repeatedly, solder joints of an electronic apparatus fatigue-fracture due to the heat stress caused by the temperature difference between the semiconductor device and the printed board. In order to remedy the fatigue failure and the deterioration of the impact resistance attributed to the partial fatigue failure, Japanese Patent Application Publication No. 2002-239780 (Japanese Patent No. 4152596) suggests using a solder alloy that has oxygen concentration in solid solution of 10 ppm or less in a non-oxidizing atmosphere such as argon gas when dissolving and mixing a tin-silver-copper type solder alloy. By way of this, ductility and strength of the solder can be improved by about 10%, and thermal fatigue resistance and the impact resistance (under the condition of simple drop test) at the solder joints can be remedied. However, the solder alloy described in said Japanese Patent Application Publication No. 2002-239780 (Japanese Patent No. 4152596) does not provide sufficient performance in view of much more rigorous impact resistance tests against accelerated gravity often conducted for miniaturized, fine, downsized semiconductor devices and electronic devices in recent years. For example, by means of only the technology of Japanese Patent Application Publication No. 2002-2397810 (Japanese Patent No. 4152596), high-temperature exposure (e.g. accelerated heat aging test in which solder alloy is left for 240 hours in a temperature-controlled bath at 150° C.) results in the generation of many Kirkendall voids near the joint interface, and no sufficient impact resistance against accelerated gravity is obtained.
As explained above, the existing solder has a drawback arising from the restrictions of its solid state ability and the joint technique. That is, when the existing solder is melted and used, an excessive amount of solder forms projections or so-called “excess volumes” at the joints that result in being subject to “leakage failure” problem by forming solder bridges toward the adjacent leads. As a result, the limits of minimization of solder-coated or solder-jointed electrode pads and leads that are formed with existing solder ball or by soaking in the existing molten solder are no more than 80 μm in width and no more than 200 μm in pitch spacing at present. Generally speaking, electronic circuits with miniature fine solder joints having the smaller width and the smaller pitch spacing have not yet been completely put to practical use, except the aforementioned electroformed solder bump. In view of this situation, further minimization of semiconductor devices and electronic devices is hampered.